KAD/DSI/104 24 channels Digital Module
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- 24 differential ended optically isolated bi-level input channels
- 24 x 32-bit counters, each counter can be programmed to operate in one of 10 different modes
- 40 ns internal resolution
- First In First Out (FIFO) based time tagging
- Resettable counters
- Independent channel programmability of falling/rising edge detection
- Detection of 0.5 μs wide input signal pulses
- Engine speed measurement
- Frequency, period, pulse width, duty cycle measurements
- Data capture from a parallel bus
- Time stamping of events
Setting up data acquisition systems can take a lot of time and effort, particularly as many systems today are growing larger and larger. Managing thousands of channels of data over dozens of data...
The KAD/DSI/102 monitors the status (high/low) of up to 24 differential-ended discrete input channels. Each of these has an assigned programmable 32-bit counter. Additionally each of the inputs can...
The KAD/MAT/101 allows you run your own programs based on a dual core C6000DSP+ARM9 microcontroller. It provides high performance DSP functions in a widely used architecture. You can develop...
24 channel, Optoisolated input counters module
The KAD/DSI/104 monitors the status (high/low) of up to 24 differential ended optically isolated input channels. Each of these has an assigned programmable 32-bit counter. Additionally each of the channels can be used to trigger time tagged events.
Each counter can be programmed to operate in one of the following modes: Period, Pulse Width, Duty Cycle, Frequency, Events Since Sample, Events Since Power Up, Events Since Reset, Time Since Event, Samples Since Power Up or Samples Since Reset. The range of each counter is programmable as is the sensitivity to the rising/falling edge. If the counter uses more than 16 bits, they are treated as two words.
All channels control time tagging to the 1K word deep FIFO (80 bits wide each word). For each input, time tagging can be triggered by a rising edge, falling edge, both edges or neither (when the channel is disabled). Every time a trigger occurs, a 80-bit word is written to the FIFO consisting of the 24 inputs (configurable to be either input state after the change or the value representing the bits which triggered the event), the 48-bit binary coded decimal IRIG time that the event happened, and FIFO flags (empty and skipped).
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